Flash memory devices are high density, non-volatile memory devices having low power consumption, fast access times and low cost. Flash memory devices are thus well suited for use in a variety of portable electronic devices that require high-density storage but cannot support a disk drive, or other mass storage devices due to high power consumption or the additional weight of such devices. An additional advantage of flash memory is that it offers in-circuit programmability. A flash memory device may thus be reprogrammed under software control while the device resides on a circuit board within an electronic device.
FIG. 1 is a flash memory cell 10 according to the prior art. The flash memory cell 10 has a metal oxide semiconductor (MOS) structure that includes a substrate 12, a pair of source/drain regions 14, a floating gate 18 overlying a MOS channel region 16, and a control gate 20 overlying the floating gate 18. An oxide structure 22 separates the floating gate 18 from the channel region 16, and also separates the floating gate 18 from the control gate 20. For the device shown, the substrate 12 is doped with P-type impurities, and the source/drain regions 14 are doped with N-type impurities.
The memory cell 10 may be programmed by applying a sufficiently positive gate voltage VCG and a positive drain voltage VD to the device 10, while maintaining the source voltage VS at a zero, or ground potential. As charge is moved to the floating gate 18 from the source/drain region 14, the device 10 attains a logic state “0”. Alternately, if little or no charge is present at the floating gate 18, a logic state corresponding to “1” is stored on the device 10.
To read the state of the device 10, a positive voltage VCG of predetermined magnitude is applied to the control gate 18, while VD is maintained positive. If the voltage applied to the control gate 18 is sufficient to turn the device 10 on, a current flows from one source/drain region 14 to the other source/drain region 14 that may be detected by other external circuits, thus indicating the logic state “1”. Correspondingly, if sufficient charge exists at the floating gate 18 to prevent the device 10 from turning on, a logic state of “0” is read. A logic state may be erased from the device 10 by applying a positive source voltage VS to the source/drain region 14 while VCG is maintained at a negative potential. The device 10 attains a logic state “1” following an erase cycle.
Although the foregoing flash memory cell 10 is highly effective to store a logic state in a memory device, it has been observed that the programming efficiency of the memory cell 10 is degraded as the number of accumulated program/erase cycles increases. As a result, the cell 10 may fail after the number of program/erase cycles exceeds a limiting value, which is termed the endurance limit for the cell 10. Although the endurance limit is relatively unimportant in cases where the cell 10 is programmed only once, it may be a critical concern where the device 10 is erased and reprogrammed numerous times. The degradation of the programming efficiency is believed to result from hot electrons that become trapped in the relatively thin oxide layer separating the floating gate 18 from the substrate 12 during a programming cycle, which permanently damages the oxide layer. In addition, extremely high electric field strengths are generated during erase cycles that cause holes having relatively low momentum to become trapped in the oxide layer separating the floating gate 18 and the substrate 12. As the cell 10 is subjected to repeated program/erase cycles, the trapped holes accumulate in the oxide layer and thus cause the electric fields applied during a read cycle to be degraded.
The qualitative effects of degradation of the flash memory cell 10 are shown in FIGS. 2-4. FIG. 2 compares the performance of a non-cycled flash memory cell 10 with the performance of the cell 10 after it has been subjected to a substantial number of erase and programming cycles. As shown in FIG. 2, the source/drain current IDS for the cycled cell 10 is significantly lower that that obtained from a non-cycled cell 10 for a comparable fixed control gate voltage VCG. As a consequence, the determination of a logic state during a read cycle is adversely affected due to the lowered source/drain current in the cycled cell 10. This effect is further shown in FIG. 3, where the source/drain current IDS of the cell 10 is observed to steadily decrease as the number of cycles accumulates on the cell 10. FIG. 3 also shows that the endurance limit for the cell 10 may occur between approximately 105 and 106 cycles.
FIG. 4 shows the variation of a threshold voltage VT for the cell 10 as the number of program/erase cycles is increased. The threshold voltage VT is defined as the minimum required voltage to turn on a cell 10 during a read cycle. In FIG. 4, VT,1 corresponds to the threshold value required to turn on the cell 10 when the floating gate of the cell 10 is charged (indicating logic state “0”), while VT,2 corresponds to the threshold value required to turn on the cell 10 when the floating gate 18 is not charged. The difference between the VT,1 and VT,2 values thus defines a threshold voltage “window”, as shown in FIG. 4. As the cell 10 is subjected to cycling, the “window” becomes progressively smaller, so that it becomes more difficult to distinguish between the two logic states stored in the cell 10.
One prior art solution to the foregoing endurance limit problem is a flash memory cell having a floating gate asymmetrically positioned towards the source, with the control gate overlying the floating gate and also directly overlying the channel region of the cell, as disclosed in detail in an article by P. Pavan, et al., entitled Flash Memories-An Overview, IEEE Proceedings, vol. 85, No. 8, pp. 1248-1271, 1997. Since the programming and erase functions occur in the portion of the channel region adjacent to the source, damage to the gate oxide is limited to only a portion of the channel region. Although the foregoing flash memory cell arrangement achieves some increase in the endurance limit, the damage to the oxide layer underlying the floating gate eventually becomes excessive, so that it is no longer possible to read the logic state stored in the cell.
Another prior art flash memory cell includes a source region that is surrounded by an N-region to further protect the source junction of the cell from the large electric field strengths that arise when the cell is erased. One significant drawback present in this configuration is that the source and drain regions may not be interchanged to extend the endurance of the cell. Further, the asymmetrical arrangement adds to the overall fabrication costs of the flash memory device.
Recently developed nitride read only memory (NROM) devices employ charge trapping in a silicon nitride layer in a non-conventional flash memory device structure. The lateral spread of charge stored in the oxide-nitride-oxide (ONO) layer compromises the ability to scale down the device's dimensions. Additionally, planar memory cells require a relatively greater area for each cell than vertical devices. There is a resulting need in the art for a flash memory device that combines the benefits of NROM cells with the benefits of vertical memory cells.